1+ months

Technical Leader Signal Integrity Engineer

Cisco Systems Inc.
San Jose, CA 95113
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What You'll Do:

Work directly with ASIC and System design teams to evaluate design trade-offs and optimize design performance / risk / cost / manufacturability

Drive next generation Serdes IP characterization

Driving next generation ASIC/system feasibility studies  

Design and analysis of multi-gigabit serial links and their compliance to standards

Electromagnetic modeling of complex 3-dimensional structures

Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs

Generating and verifying PCB layout rules

Performing DDR4 static timing and signal integrity analysis

Modeling and analyzing power delivery networks

Performing physical measurements to collect data for design validation and simulation correlations

Driving methodology improvements and automation - improving performance and efficiency

Development simulation tools with EDA vendor(s) whenever needed for analysis.

Mentor junior engineers and interns

Who You'll Work With:

Cisco CHG SI team is seeking a signal integrity engineer for design and analysis of high-speed interfaces and power distribution network. You will be part of CHG signal integrity team developing the Next Generations of Cisco Switch products, participate in the definition and design of current and next generation ASIC, package, printed circuit board (PCB), and system interconnect. The individual will be part of a larger team working closely with system architects, logic designers, ASIC engineers, CAD engineers and other very hardworking and knowledgeable SI engineers in creation of next generation high performance networking products.

Who You Are:

Self-motivation, Strong teamwork, Strong communication skills and Out of the box thinking with the strong desire to innovate are meaningful.

Work experience with high speed NRZ and PAM4 Serdes, PLLs, CDR and FEC

Hands on experience with ASIC development focused on Serdes, DDR4 and IO IP selection, package design and simulation, ASIC level power integrity

In depth knowledge of the IEEE 802.3 and OIF specifications for 25Gbps and 56Gbps Serdes Interfaces

Hands on experience with a broad range PCB materials, understanding cost/performance trade offs

Knowledge of DDR4 simulation methodology and timing analysis

Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis)

Well versed with 3-D field solvers

In depth understanding of electromagnetic theory is required

Working knowledge of AMI models and tools (SiSoft QCD and ADS)

Strong lab skills and measurement experience are required (VNA, TDR, Real Time Scope, BERT)

Strong tools knowledge (HFSS, ADS, SiSoft QCD and QSI, Cadence PowerSI/DC, Allegro, Simbeor, HSpice)

Generating the routing requirements and electrical margins for specific interfaces and verifying their correctness

Ability to define a project schedule and requirements, then deliver to that schedule

Educational Background

PhD/MSEE combined with 1-2+ years of related experience, or BSEE combined with 3-5+ years related experience.

Posted: 2021-03-17 Expires: 2021-05-17
Sponsored by:
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Technical Leader Signal Integrity Engineer

Cisco Systems Inc.
San Jose, CA 95113
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