1+ months

Sr. ASIC design verification engineer.

Cisco Systems Inc.
台北市, T'ai-Pei Shih 110
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5 - 10 years in ASIC design verification.

Hands-on experience on Verilog HDL verification

Experience of high performance ASIC design flow from specification to system bringing up

Knowledge of System Verilog and UVM verification methodology

Highly motivated, positive, detail oriented and responsible

Good team player and good communication skills

MSEE/MSCS

#LI-APJJS1


Posted: 2020-09-18 Expires: 2020-12-31
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Sr. ASIC design verification engineer.

Cisco Systems Inc.
台北市, T'ai-Pei Shih 110
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