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Senior DFT Design and Automation Engineer (Austin, TX)

Qualcomm Inc.
San Diego, CA 92101
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Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Job Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

GENERAL SUMMARY

DFTCAD Design for Test CAD part of Global CAD organization working on latest technology offering from EDA Vendors and develop in house tools, flows.

Job duties:

Own DFT Scan insertion flows, ATPG flows for Global SoC organization. Work closely with cross-functional teams, EDA vendors, and other team members to develop best in class flow enabling the PPAY (Power, Performance, Area and Yield) targets for Qualcomm chipsets
Candidate would be working on scan insertion flows across tool sets Genus, DCNXT, Fusion Compiler with focus on developing technologies and/or methodologies to directly impact the PPAY (Power, Performance, Area, Yield) of Qualcomm chipsets.
Candidate would be working on latest cutting-edge technology nodes
Candidate would work on ATPG flows across Tessent and Synopsys Tetramax toolset
Candidate would work hands on to develop technologies / methodologies related to DFT, which can improve QTI competitiveness and provide higher value proposition for our product chips.
Candidate would also work on integrating / deploying these technologies and flows in product chips by working with GCAD teams, enablement team, DTECH team, product SoC team.

Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field.
7+ years ASIC design, verification, or related work experience.

Required:
Bachelor's degree in EE/CS/CE with 8+ years or Masters degree in EE/CS/CE with 5+ years of industry experience in one of the following areas:

1. DFT (Design for Test) with focus on scan insertion, ATPG
2. Knowledge of Timing constraints, SDC generating test constraints
3. RTL Design, Architecture, SoC design flow knowledge from RTL to GDS
4. Automation in TCL, Python or Perl
5. Expertise in Genus, DCNXT and/or Fusion Compiler need competency in atleast one of these 3 tools

Preferred Qualifications:
ASIC Design knowledge and experience in::
DFT (Design for Test)
Front-end design
Post Silicon debug

Good knowledge of scripting tools/languages perl, TCL and/or Python.

Education Requirements:

Required: Bachelors/Master's in Electrical Engineering and/or Computer Engineering and/or Computer Science and/or with > 8 year of work experience

Keywords: DFTCAD, Design for Test, ATPG, DFT Scan,

Physical Requirements
Frequently transports between offices, buildings, and campuses up to mile.
Frequently transports and installs equipment up to 5 lbs.
Performs required tasks at various heights (e.g., standing or sitting).
Monitors and utilizes computers and test equipment for more than 6 hours a day.
Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

DFTCAD Design for Test CAD part of Global CAD organization working on latest technology offering from EDA Vendors and develop in house tools, flows.

Job duties:

Own DFT Scan insertion flows, ATPG flows for Global SoC organization. Work closely with cross-functional teams, EDA vendors, and other team members to develop best in class flow enabling the PPAY (Power, Performance, Area and Yield) targets for Qualcomm chipsets

  • Candidate would be working on scan insertion flows across tool sets Genus, DCNXT, Fusion Compiler with focus on developing technologies and/or methodologies to directly impact the PPAY (Power, Performance, Area, Yield) of Qualcomm chipsets.
  • Candidate would be working on latest cutting-edge technology nodes
  • Candidate would work on ATPG flows across Tessent and Synopsys Tetramax toolset
  • Candidate would work hands on to develop technologies / methodologies related to DFT, which can improve QTI competitiveness and provide higher value proposition for our product chips.
  • Candidate would also work on integrating / deploying these technologies and flows in product chips by working with GCAD teams, enablement team, DTECH team, product SoC team.

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field.

7+ years ASIC design, verification, or related work experience.

Required:

Bachelor's degree in EE/CS/CE with 8+ years or Masters degree in EE/CS/CE with 5+ years of industry experience in one of the following areas:

1. DFT (Design for Test) with focus on scan insertion, ATPG

2. Knowledge of Timing constraints, SDC generating test constraints

3. RTL Design, Architecture, SoC design flow knowledge from RTL to GDS

4. Automation in TCL, Python or Perl

5. Expertise in Genus, DCNXT and/or Fusion Compiler need competency in atleast one of these 3 tools

Preferred Qualifications:

ASIC Design knowledge and experience in::

  • DFT (Design for Test)
  • Front-end design
  • Post Silicon debug

Good knowledge of scripting tools/languages perl, TCL and/or Python.

Education Requirements:

  • Required: Bachelors/Master's in Electrical Engineering and/or Computer Engineering and/or Computer Science and/or with > 8 year of work experience

Keywords: DFTCAD, Design for Test, ATPG, DFT Scan,

Physical Requirements

Frequently transports between offices, buildings, and campuses up to mile.

Frequently transports and installs equipment up to 5 lbs.

Performs required tasks at various heights (e.g., standing or sitting).

Monitors and utilizes computers and test equipment for more than 6 hours a day.

Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Minimum Qualifications

Education:

Work Experiences:

Certifications:

Skills:

Preferred Qualifications

Education:

Work Experiences:

Certifications:

Skills:

Applicants: If you are an individual with a disability and need an accommodation during the application/hiring process, please call Qualcomms toll-free number found here for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm is an equal opportunity employer and supports workforce diversity.

To all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

If you would like more information about this role, please contact Qualcomm Careers.


We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goalwe invent breakthrough technologies that transform how the world connects, computes, and communicates.

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Posted: 2021-06-11 Expires: 2021-07-12
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Senior DFT Design and Automation Engineer (Austin, TX)

Qualcomm Inc.
San Diego, CA 92101

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