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ASIC Synthesis Staff Specialist- Turing

Qualcomm Inc.
Bangalore
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Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

Job Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

GENERAL SUMMARY

Responsibilities include but not limited to

Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
Work closely with RTL design, DFT, PD Implementation, Power teams to optimize Performance, Power and Area (PPA) for best PPA
Proficient in constraint generation and validation.
Tabulate metrics results for analysis comparison.
Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
Help all team members in resolving their technical queries and keep project on track.
Develop new flow and methodologies to keep improving QOR.

Minimum Requirements
7-12 years of experience in ASIC Physical synthesis/STA
Expertise in Synopsys/Cadence Synthesis tools
Expertise with STA with prime time/Tempus.
Good Experience in synthesis timing closure and interactions with DFT and PD.
Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
Experience in formal verification with Cadence LEC
Expertise in ECO flows using conformal/Formality ECO.
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in RTL HDL languages Verilog/VHDL.
Understanding of RTL to GDS flow
Expertise in Perl, TCL language
Excellent collaboration skill with all stakeholders is must.
Excellent communication skills are must.

Responsibilities include but not limited to

  • Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
  • Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
  • Work closely with RTL design, DFT, PD Implementation, Power teams to optimize Performance, Power and Area (PPA) for best PPA
  • Proficient in constraint generation and validation.
  • Tabulate metrics results for analysis comparison.
  • Develop Rapid Physical synthesis Convergence Methodologies and Automation for optimal PPA.
  • Help all team members in resolving their technical queries and keep project on track.
  • Develop new flow and methodologies to keep improving QOR.

Minimum Requirements

  • 7-12 years of experience in ASIC Physical synthesis/STA
  • Expertise in Synopsys/Cadence Synthesis tools
  • Expertise with STA with prime time/Tempus.
  • Good Experience in synthesis timing closure and interactions with DFT and PD.
  • Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
  • Experience in formal verification with Cadence LEC
  • Expertise in ECO flows using conformal/Formality ECO.
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in RTL HDL languages Verilog/VHDL.
  • Understanding of RTL to GDS flow
  • Expertise in Perl, TCL language
  • Excellent collaboration skill with all stakeholders is must.
  • Excellent communication skills are must.

Minimum Qualifications

Education:

Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems

Work Experiences:

5+ years Hardware Engineering experience or related work experience.

Certifications:

Skills:

Preferred Qualifications

Education:

Masters - Computer Science, Masters - Engineering, Masters - Information Systems

Work Experiences:

8+ years Hardware Engineering experience or related work experience. ,2+ years experience with circuit design (e.g., digital, analog, RF). ,2+ years experience utilizing schematic capture and circuit simulation software. ,2+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. ,1+ years in a technical leadership role with or without direct reports.

Certifications:

Skills:

Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email toaccommodationsupport

To all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact Qualcomm Careers.


We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goalwe invent breakthrough technologies that transform how the world connects, computes, and communicates.

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Posted: 2021-06-11 Expires: 2021-07-12
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ASIC Synthesis Staff Specialist- Turing

Qualcomm Inc.
Bangalore

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