Senior ASIC Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    Cloud and Data Center, Networking
  • Job Id
    1228471
New

Cisco is always looking to identify talented people, especially ASIC Engineers to join our market-leading Datacenter Networking ASIC team. Be a part of shaping Cisco’s revolutionary solutions for datacenters by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, HW, SW, telemetry, security, etc).  Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!.


You will collaborate closely with the architecture, hardware, and software teams to design, develop, verify, and validate Data Center networking ASICs working across product generations, networking technologies, and protocols. There are only a handful of teams in the world that implement and deliver successful ASICs at this performance and scale, and we take pride in the impact of our work. Every time you access the internet, chances are, your data is going through one of our ASICs.

Responsibilities:

  • Develop high-performance ASICs from specification to tape-out, including RTL, synthesis, physical design, and timing closure
  • Maintain and enhance existing designs using Verilog/SystemVerilog
  • Implement new designs using Verilog/SystemVerilog
  • Triage and troubleshoot failures down to the root cause
  • Actively work with the verification team to deliver ASICs with high quality
  • Actively work with the physical design team to resolve implementation and timing issues
  • Develop tests and debug ASICs in the emulation
  • Perform diagnostics and tests for ASICs in the lab

Education and Experience Required:

  • Bachelor’s or Master’s degree in Electrical Engineering
  • 8-12 years of ASIC design and verification experience

Knowledge and Skills:

  • Excellent Verilog and SystemVerilog programming and debugging skills
  • Scripting expertise (Python, Perl, TCL, shell programming)
  • Excellent knowledge of synthesis constraints
  • Excellent knowledge of physical design and implementation to achieve timing closure
  • Ability to write and debug test
  • Ability to debug system-wide issues
  • Create documentation and help with guidelines/specs
  • Good written and verbal communication skills
  • Collaborative and team-focused with the drive to learn and grow

 

 

 *LI-PC1
dicedev
#GD2015

 

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Senior ASIC Engineer

Cisco Systems Inc.
San Jose, US

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